By Yoonjin Kim
Coarse-grained reconfigurable structure (CGRA) has emerged as an answer for versatile, application-specific optimization of embedded structures. assisting you already know the problems all for designing and developing embedded structures, Design of Low-Power Coarse-Grained Reconfigurable Architectures bargains new frameworks for optimizing the structure of elements in embedded platforms so one can reduce zone and store strength. genuine software benchmarks and gate-level simulations substantiate those frameworks.
The first half the booklet explains find out how to decrease energy within the configuration cache. The authors current a low-power reconfiguration approach in keeping with reusable context pipelining that merges the concept that of context reuse into context pipelining. additionally they suggest dynamic context compression able to assisting required bits of the context phrases set to let and the redundant bits set to disable. additionally, they speak about dynamic context administration for decreasing energy intake within the configuration cache by way of controlling a read/write operation of the redundant context words.
Focusing at the layout of an economical processing aspect array to minimize zone and gear intake, the second one half the textual content offers a cheap array cloth that uniquely rearranges processing components and their interconnection designs. The booklet additionally describes hierarchical reconfigurable computing arrays including reconfigurable computing blocks with sorts of verbal exchange constitution. the 2 computing blocks proportion severe assets, supplying an effective conversation interface among them and lowering the general quarter. the ultimate bankruptcy takes an built-in method of optimization that pulls at the layout schemes provided in previous chapters. utilizing a case examine, the authors reveal the synergy impact of mixing a number of layout schemes.